The H-cat photonic quantum computer, where loss becomes a heralded erasure.
A hybrid CV-DV architecture: each logical qubit pairs a bosonic cat with a single photon. When a photon is lost, the cat parity flips, so loss is caught and located, not a silent unknown error. That is the advantage, made visible below.
One H-cat logical qubit, live
Mode A is a cat (amber); Mode B is a single photon in dual-rail (cyan). Inject a loss and watch.
The same loss that breaks other photonic qubits is the H-cat's error signal.
- Usable cats at 3.5 to 8 dB squeezing
- Deterministic hybrid fusion, conditioned on the herald
- Photon loss flips parity: loss = heralded erasure
- Erasures correct far more cheaply than silent errors
- Needs 10+ dB squeezing, hard to reach on chip
- Grid-state preparation is demanding
- Loss degrades the grid as a silent shift error
- Probabilistic fusion: most attempts fail
- Heavy multiplexing to reach near-deterministic gates
- Loss removes the photon, costing the qubit outright
Numbers reflect full circuit-level noise (noisy syndrome extraction), superseding earlier phenomenological figures. The machine is operated at a 0.4 to 0.5 percent per-cycle loss spec to leave margin below the threshold.
From concept to device spec, in the browser and in Python.
SDK / Run a Circuit
Build a gate-model circuit, run it on the H-cat simulator, see counts, resource estimates, and the heralded-erasure fraction.
Resource Analyzer
Turn a target into a device spec: code distance, cats per logical, qubits per rack, with the corrected 0.79% threshold.
Workbench
Open-source Python SDK: cat states, breeding, hybrid fusion, loss models, and fault tolerance.
Fusion Designer
Lay out H-cat qubits and deterministic fusion networks on a canvas. Export and import designs as JSON.
Docs
Architecture, the validation campaign, and how each tool works, end to end.
Education
Short lessons on cat qubits, squeezing, breeding, fusion, and fault tolerance.
Pre-hardware, but every claim is simulation-validated.
Two independent codebases (QuTiP and Strawberry Fields) agree on cat fidelity to 4e-5.
Full circuit-level error correction: noisy syndrome extraction with stim and PyMatching.
3D EM plus fabrication Monte Carlo: 99 percent yield with adequate thermal tuner authority.
Test chip QF-TC1: 5x5 mm tile, 22 structures, DRC clean (0 violations) on a foundry-neutral stand-in deck.
pip install dyber and pip install dyberforge both work today, Apache-2.0. SDK on GitHub.
Honest status: hardware is in development and the hcat_qpu backend is not yet available. Circuits run on the physics-informed local simulator. Resource numbers are estimates calibrated to the June 2026 campaign, not guarantees. Dyber, Inc.