Component simulations

Component simulations.

No Dyber hardware exists, and nothing on this page is a measurement. These are component-level simulations: each one checks a single piece (cat generation, ring fabrication, a chip layout). They do not show that a fault-tolerant H-cat machine is buildable. The figures come from Dyber's simulation code; the public SDK on PyPI covers small-cat generation and the resource model.

Independent cross-check

Independent cross-check, two codebases

Small-cat fidelity (one photon subtracted from squeezed vacuum, 0.5 to 8 dB) computed two ways: once in QuTiP, once in a fully independent Strawberry Fields implementation. The largest difference is about 4e-5, far inside the 1e-2 target. This is a component simulation: it checks the cat-generation code across two quantum-optics stacks, not the machine.

Small-cat fidelity computed by QuTiP and by an independent Strawberry Fields implementation, overlaid, with their absolute difference; the largest difference is about 4e-5.

crosscheck.png · QuTiP vs Strawberry Fields · small cats, max difference ~4e-5, target 1e-2 · component simulation

Ring fabrication

Simulated resonance-spec yield of a ring resonator from a 3D electromagnetic and fabrication Monte Carlo versus thermal tuner range, for two waveguide geometries; the better geometry reaches about 99 percent with plus or minus 2 to 3 nm of tuner range.

fab-yield.png · 3D EM + fabrication Monte Carlo · yield vs thermal tuner range · component simulation

Ring fabrication Monte Carlo (component simulation)

In simulation, a 3D electromagnetic model fed through a fabrication Monte Carlo gives a ring resonance-spec yield of about 99 percent once the thermal tuners have +/- 2 to 3 nm of range, for the better of the two simulated waveguide geometries. The simulation points to tuner range, not tighter lithography, as the yield lever. It covers ring resonances only.

Test chip layout

Test chip layout, QF-TC1

QF-TC1 is a 5x5 mm test chip layout with 22 structures and 0 violations against a foundry-neutral stand-in rule deck. It is design-rule clean only against that stand-in deck, and it has not been fabricated. Each structure targets one component-level simulation result.

Layout of the QF-TC1 test chip: a 5 by 5 mm tile holding 22 test structures, with zero violations against a foundry-neutral stand-in rule deck only.

qf-tc1.png · 5x5 mm, 22 structures · 0 violations, stand-in rule deck only · not fabricated

Run the model

Run the model yourself.

The illustrative simulator and the resource model ship in the SDK. Install it and print the model resource report for a circuit.

Install

pip install dyber

Build a circuit and read its resources

from dyber import Dyber, Circuit

c = Circuit(2); c.h(0); c.cx(0, 1); c.measure_all()
dy = Dyber()
job = dy.backend("local_simulator").run(c, shots=1000)
print(job.result().resources)

This prints the model resource report (code distance, cats per logical qubit and the loss split). Model values: abstract circuit model with assumed loss heralds. Not a hardware operating point. The same model powers the Resource Analyzer and is open source in the dyberforge package.

Methods and tooling

The actual stack.

QuTiP and Strawberry Fields : quantum optics, cross-checked against each other for small-cat fidelity.
stim and PyMatching : Dyber's research surface-code runs use them in an abstract circuit model with assumed loss heralds; the SDK's resource model uses a fit to those runs. Model value: abstract circuit model with assumed loss heralds. Not a hardware operating point.
Meep and MPB : 3D electromagnetics and mode solving for the photonic structures.
gdsfactory and KLayout : layout generation and DRC for the QF-TC1 test chip layout (stand-in rule deck).