Target to device spec
Enter a target logical error rate, physical noise, and device constraints. The analyzer converts your spec into a complete device bill: code distance, cat states per logical qubit, physical qubits per rack, and total hardware footprint.
Device Spec
Enter parameters and click Estimate.
Validation panel
Numbers a reviewer can check directly against the June 2026 circuit-level validation campaign:
- Circuit-level fault-tolerance threshold 0.79 to 0.90 percent loss per cycle, measured under full circuit-level noise (noisy syndrome extraction) with stim and PyMatching.
- Two independent codebases (QuTiP and Strawberry Fields) agree on cat fidelity to 4e-5.
- Master-equation (mesolve) evolution agrees with the closed-form loss channel to 1e-9.
- End-to-end digital twin runs from device parameters (ring Q, pump power, TES efficiency) through to logical error in one continuous density-matrix pipeline.
- A pytest regression suite pins every headline number (9 passed: 6 historical, 3 new v2 pins).
Calibrated to the June 2026 circuit-level validation campaign: at the 0.5 percent per-cycle loss spec this gives p_erase 1.88 percent, p_pauli 6.0e-4, distance 53, 5,617 cats per logical, identical to the validated v2 resource model (circuit-level loss threshold 0.79 percent per cycle corrected, 0.898 percent uncorrected). Numbers reflect full circuit-level noise (June 2026 campaign), superseding earlier phenomenological figures. Estimates, not guarantees. See the docs for methodology and assumptions.